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May 1997
ML4819 Power Factor and PWM Controller "Combo"
GENERAL DESCRIPTION
The ML4819 is a complete boost mode Power factor Controller (PFC) which also contains a PWM controller. The PFC circuit is similar to the ML4812 while the PWM controller can be used for current or voltage mode control for a second stage converter. Since the PWM and PFC circuits share the same oscillator, synchronization of the two stages is inherent. The outputs of the controller IC provide high current (>1A peak) and high slew rate to quickly charge and discharge MOSFET gates. Special care has been taken in the design of the ML4819 to increase system noise immunity. The PFC section is of the peak current sensing boost type, using a current sense transformer or current sensing MOSFETs to non-dissipatively sense switch current. This gives the system overall efficiency over average current sensing control method. The PWM section includes cycle by cycle current limiting, precise duty cycle limiting for single ended converters, and slope compensation.
FEATURES
s s s s s s s
Large oscillator amplitude for better noise immunity Precision duty cycle limit for PWM section Current input gain modulator improves noise immunity Programmable Ramp Compensation circuit Over-Voltage comparator helps prevent output "runaway"
BLOCK DIAGRAM
10
20
CT RAMP COMP SLOPE COMPENSATION
l4
M
e
Se
-
R
3 2
GM OUT OVP
S
Q
+ -
5V
e
4 5
EA OUT A INV A 5V
+ -
ea s
ERROR AMP
IEA
R VCC OUT A S Q PGND A
16 17
Pl
6 19
ISINE
GAIN MODULATOR IMULT
GND
+
5V
-
-
1
ISENSE A
+
POWER FACTOR CONTROLLER
+
12
+
-
RT
82
4
OSC
fo
PWM CONTROLLER
rN
ew
-
Wide common mode range in current sense compensators for better noise immunity Under-Voltage Lockout circuit with 6V hysteresis
De
1V 0.7V VCC UNDER VOLTAGE LOCKOUT
DUTY CYCLE ILIM
si gn
7 11
s
ISENSE B
9
PWM B
8
OUT B PGND B
14 13
VREF VCC
18 15
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s
s
Two 1A peak current totem-pole output drivers Precision buffered 5V reference (1%)
ML4819
PIN CONFIGURATION
ML4819 20-Pin PDIP
ISENSE A OVP GM OUT EA OUT A INV A ISINE DUTY CYCLE PWM B ISENSE B RT
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
CT GND VREF PGND A OUT A VCC OUT B PGND B RAMP COMP ILIM
TOP VIEW
PIN DESCRIPTION
PIN NAME FUNCTION PIN NAME FUNCTION
1
ISENSE A
Input form the PFC current sense transformer to the PWM comparator (+). Current Limit occurs when this point reaches 5V. Input to Over-Voltage comparator. Output of Gain Modulator. A resistor to ground on this pin converts the current to a voltage. Output of error amplifier.
11 ILIM
Cycle by cycle PWM current limit. Exceeding 1V threshold on this pin terminates the PWM cycle.
2 3
OVP GM OUT
12 RAMP COMP Buffered output from the Oscillator Ramp (CT). A resistor to ground sets a current, 1/2 of which is sourced on pins 9 and 11. 13 GND B 14 OUT B Return for the high current totem pole output of the PWM controller. PWM controller totem pole output. Positive Supply for the IC. PFC controller totem pole output. Return for the high current totem pole output of the PFC controller. Buffered output for the 5V voltage reference Analog signal ground. Timing Capacitor for the Oscillator.
4 5 6 7 8 9
EA OUT A INV A ISINE
Inverting input to error amplifier. Current Multiplier input. 15 VCC 16 OUT A 17 GND A 18 VREF 19 GND 20 CT
DUTY CYCLE PWM controller duty cycle is limited by setting this pin to a fixed voltage. PWM B ISENSE B Error voltage feedback input. Input for Current Sense resistor for current mode operation or for Oscillator ramp for voltage mode operation. Oscillator timing resistor pin. A 5V source across this resistor sets the charging current for CT
10 RT
2
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ML4819
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Supply Voltage (VCC) ................................................. 35V Output Current, Source or Sink (RAMP COMP) DC ....................................................................... 1.0A Output Energy (capacitive load per cycle) ................... 5J Multiplier ISINE Input (ISINE) ................................... 1.2mA Error Amp Sink Current (GM OUT) ........................ 10mA Oscillator Charge Current ........................................ 2mA Analog Inputs (ISENSE A, EA OUT A, INV A) ............................................................... -0.3V to 5.5V Junction Temperature ............................................. 150C Storage Temperature Range ..................... -65C to 150C Lead Temperature (soldering 10 sec.) ..................... 260C Thermal Resistance (JA) Plastic DIP or SOIC ......................................... 60C/W
OPERATING CONDITIONS
Temperature Range ML4819C .................................................. 0C to 70C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, RT = 14k, CT = 1000pF, TA = Operating Temperature Range, VCC = 15V (Notes 1, 2).
PARAMETER OSCILLATOR Initial Accuracy Voltage Stability Temperature Stability Total Variation Ramp Valley Ramp Peak RT Voltage Discharge Current (PWM B open) TJ = 25C, VOUT A = 2V VOUT A = 2V DUTY CYCLE LIMIT COMPARATOR Input Offset Voltage Input Bias Current Duty Cycle REFERENCE Output Voltage Line Regulation Load Regulation Temperature Stability Total Variation Output Noise Voltage Long Term Stability Short Circuit Current ERROR AMPLIFIER Input Offset Voltage Input Bias Current Open Loop Gain PSRR Output Sink Current Output Source Current REV. 1.0 10/10/2000 1 < VEA OUT A < 5V 12V < VCC < 25V VEA OUT A = 1.1V, VINV A = 5.2V VEA OUT A = 5.0V, VINV A = 4.8V 60 60 2 -0.5 -15 -0.1 75 90 12 -1.0 15 -1.0 mV A dB dB mA mA Line, load, temperature 10Hz to 10kHz TJ = 125C, 1000 hours, (Note 1) VREF = 0V -30 4.9 50 5 -85 25 -180 TJ = 25C, IO = 1mA 12V < VCC < 25V 1mA < IO < 20mA 4.95 5.00 2 8 0.4 5.1 5.05 20 25 V mV mV % V V mV mA VDUTY CYCLE = VREF/2 43 -15 -2 45 15 -10 49 mV A % 4.8 7.5 7.2 Line, temp. 88 0.9 4.3 5.0 8.4 8.4 5.2 9.3 9.5 TJ = 25C 12V < VCC < 18V 90 97 0.2 2 106 104 kHz % % kHz V V V mA mA CONDITIONS MIN TYP MAX UNITS
3
ML4819
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER ERROR AMPLIFIER (continued) Output High voltage Output Low Voltage Unity Gain Bandwidth GAIN MODULATOR ISINE Input Voltage Output Current (GM OUT) ISINE = 500A ISINE = 500A, INV A = VREF -20mV ISINE = 500A, INV A = VREF + 20mV ISINE = 1mA, INV A = VREF - 20mV Bandwidth PSRR SLOPE COMPENSATION CIRCUIT RAMP COMP Voltage IOUT (ISENSE A or ISENSE B) OVP COMPARATOR Input Offset Voltage Hysteresis Input Bias Current Propagation Delay ISENSE COMPARATORS Input Common Mode Range Input Offset Voltage ISENSE A ISENSE B Input Bias Current Input Offset Current Propagation Delay ILIMIT (A) Trip Point ILIM COMPARATOR ILIMIT Trip Point Input Bias Current Propagation Delay OUTPUT DRIVERS Output Voltage Low IOUT = -20mA IOUT = -200mA Output Voltage High IOUT = 20mA IOUT = 200mA Output Voltage Low in UVLO Output Rise/Fall Time IOUT = -1mA, VCC = 8V CL = 1000pF 13 12 0.1 1.6 13.5 13.4 0.1 50 0.8 0.4 2.2 V V V V V ns .95 1.0 -2 150 1.05 -10 V A ns VOVP = 5.5V 4.8 -3 -0.2 -15 0.4 0.7 -3 0 150 5 5.2 5.5 15 0.9 -10 3 V mV V A A ns V Output Off Output On -15 100 120 -0.3 150 15 140 -3 mV mV A ns IRAMP COMP = 100A (Note 3) 45 VC(T) - 1 48 51 V A 12V < VCC < 25V 900 0.4 460 0.7 495 0 990 200 70 0.9 505 10 1005 V A A A kHz dB IEA OUT A = -0.5mA, VINV A = 4.8V IEA OUT A = 2mA, VINV A = 5.2V 6.5 7.0 0.7 1.0 1.0 V V MHz CONDITIONS MIN TYP MAX UNITS
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ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER UNDER-VOLTAGE LOCKOUT Start-Up Threshold Shut-Down Threshold VREF Good Threshold SUPPLY Supply Current Start-Up, VCC = 14V Operating, TJ = 25C
Note 1: Note 2: Note 3: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. VCC is raised above the Start-Up Threshold first to activate the IC, then returned to 15V. PWM comparator bias currents are subtracted from this reading.
CONDITIONS
MIN
TYP
MAX
UNITS
15 9
16 10 4.4
17 11
V V V
0.6 25
1.2 35
mA mA
FUNCTIONAL DESCRIPTION
OSCILLATOR The ML4819 oscillator charges the external capacitor (CT) with a current (ISET) equal to 5/RSET. When the capacitor voltage reaches the upper threshold, the comparator changes state and the capacitor discharges to the lower threshold through Q1. While the capacitor is discharging, the clock provides a high pulse. The oscillator period can be described by the following relationship:
20 DUTY CYCLE
+5V
7
+ -
TO PWM LATCH B
ISET 10 RT
5V VREF ISET
+ -
CLOCK
tOSC = tRAMP + tDEADTIME where:
t RAMP = C(Ramp Valley to Peak) ISET
C(Ramp Valley to Peak) 8.4mA - ISET
CT 8.4mA Q1
TO PWM LATCHES
and:
t DEADTIME =
CLOCK tD RAMP PEAK CT RAMP VALLEY
The maximum duty cycle of the PWM section can be limited by setting a threshold on pin 7. when the CT ramp is above the threshold at pin 7, the PWM output is held off and the PWM flip-flop is set:
DLIMIT
where:
D x (VPIN7 - 0.9) OSC 3.4
DLIMIT = Desired duty cycle limit DOSC = Oscillator duty cycle
Figure 1. Oscillator Block Diagram
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ML4819
AVOL, OPEN-LOOP VOLTAGE GAIN (dB)
50 VCC = 15V TA = 25 C 95%
100 80 GAIN 60 40 PHASE 20 0 -20 10 100 1.0k 10k 100k f, FREQUENCY (Hz) 1.0M VCC = 15V VO = 1.0V TO 5.0V RL = 100k TA= 25 C
0 , EXCESS PHASE (DEGREES) -30 60 90 120 150 180 10M
RT, TIMING RESISTOR (k)
30
10 20 0p F
0p
F
90%
20
1n
10 8
50 F
0p
F
85%
2n 5n F
F
5
10
nF
3 20
30
50
100
200
300
500
fOSC, OSCILLATOR FREQUENCY (kHz) MAX DUTY CYCLE
Figure 2. Oscillator Timing Resistance vs. Frequency
Figure 5. Error Amplifier Open-Loop Gain and Phase vs Frequency GAIN MODULATOR
0
VSAT, OUTPUT SATURATION VOLTAGE (V)
VCC -1.0 -2.0
SOURCE SATURATION (LOAD TO GROUND)
VCC = 15V 80s PULSED LOAD 120 Hz RATE
TA = 25 C
The ML4819 gain modulator is a linear current input multiplier to provide high immunity to the disturbances caused by high power switching. The rectified line input sine wave is converted to a current via a dropping resistor. In this way, small amounts of ground noise produce an insignificant effect on the reference to the PWM comparator. The output of the gain modulator is a current of the form:
3.0 2.0 1.0 0 TA = 25 C SINK SATURATION (LOAD TO VCC) GND 0 200 400 600 800
IOUT is proportional to ISINE x IEA where ISINE is the current in the dropping resistor, and IEA is a current proportional to the output of the error amplifier. When the error amplifier is saturated high, the output of the gain modulator is approximately equal to the ISINE input current. The gain modulator output current is converted into the reference voltage for the PWM comparator through a resistor to ground on the gain modulator output. The gain modulator output is clamped to 5V to provide current limiting.
IO, OUTPUT LOAD CURRENT (mA)
Figure 3. Output Saturation Voltage vs. Output Current
ERROR AMPLIFIER The ML4819 error amplifier is a high open loop gain, wide bandwidth amplifier.
+5V + 0.5mA
+8V
ISINE 6 IERR ERROR VOLTAGE 9V GAIN MODULATOR
4
INV
-
ISINE
IERR
3
EA OUT
3
MULTIPLIER
Figure 4. Error Amplifier Configuration 6
Figure 6. Gain Modulator Block Diagram
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ML4819
SLOPE COMPENSATION Slope compensation is accomplished by adding 1/2 of the current flowing out of pin 12 to pin 1 (for the PFC section and pin 9 (for the PWM section). The amount of slope compensation is equal to (IRAMP COMP/2) x RL where RL is the impedance to GND on pin 1 or pin 9. Since most of the PWM applications will be limited to 50% duty cycle, slope compensation should not be needed for the PWM section. This can be defeated by using a low impedance load to the current sense on pin 9.
10 20 RT CT VREF IR(SC) Q1 RAMP COMP 12 RSC SLOPE COMPENSATION IR(SC) 2 9V IR(SC) 2 TO PIN 9
ICC, SUPPLY CURRENT (mA)
40
ENABLE VREF VREF GEN. 9V - + INTERNAL BIAS VCC 5V VREF
OSC
Figure 9. Under-Voltage Lockout Block Diagram
TO PIN 1
30
20
Figure 7. Slope Compensation Circuit
10 TA = 25 C 0
500
MULTIPLIER OUTPUT CURRENT (A)
4.5V 4.0V 3.5V 3.0V
300
E/A OUTPUT VOLTAGE (V)
400
0
10
20 VCC, SUPPLY VOLTAGE (V)
30
40
Figure 10a. Total Supply Current vs. Supply Voltage
200 2.5V 100 2.0V 1. 5V 0 100 200 300 SINE INPUT CURRENT (A) 400 500
0
35 30
Figure 8. Gain Modulator Linearity
ICC -- SUPPLY CURRENT
25 20 15 10 5
UNDER VOLTAGE LOCKOUT On power-up the ML4819 remains in the UVLO condition; output low and quiescent current low. The IC becomes operational when VCC reaches 16V. When VCC drops below 10V, the UVLO condition is imposed. During the UVLO condition, the 5V VREF pin is "off", making it usable as a status flag.
OPERATING CURRENT
START-UP 0 0 10 20 30 40 50 60 70
TEMPERATURE ( C)
Figure 10b. Supply Current (ICC) vs. Temperature
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ML4819
VREF, REFERENCE VOLTAGE CHANGE (mV)
0 VCC = 15V -4.0 -8.0
Where DON is the duty cycle [TON/(TON + TOFF)]. The input boost inductor will dry out when the following condition is satisfied: VIN(t) < VOUT x 1- DON(MAX) or
[
]
(2)
-12 -16 -20 -24 TA = 25 C
VINDRY = 1- DON(MAX) x VOUT
[
]
(3)
VINDRY: Voltage where the inductor dries out. VOUT: Output dc voltage.
120
0
20
40
60
80
100
IREF, REFERENCE SOURCE CURRENT (mA)
Figure 11. Reference Load Regulation
Effectively, the above relationship shows that the resetting volt-seconds are more than setting volt-seconds. In energy transfer terms this means that less energy is stored in the inductor during the ON time than it is asked to deliver during the OFF time. The net result is that the inductor dries out. The recommended maximum duty cycle is 95% at 100KHz to allow time for the input inductor to dump its energy to the output capacitors. For example: if: VOUT = 380V and DON(MAX) = 0.95 then substituting in (3) yields VINDRY = 20V. The effect of drying out is an increase in distortion at low input voltages. For a given output power, the instantaneous value of the input current is a function of the input sinusoidal voltage waveform. As the input voltage sweeps from zero volts to its maximum value and back, so does the current. The load of the power factor regulator is usually a switching power supply which is essentially a constant power load. As a result, an increase in the input voltage will be offset by a decrease in the input current. By combining the ideas set forth above, some ground rules can be obtained for the selection and design of the input inductor: Step 1: Find minimum operating current.
IIN(MIN)PEAK = 1.414 x PIN(MIN) VIN(MAX)
APPLICATIONS
POWER FACTOR SECTION The power factor section in the ML4819 is similar to the power factor section in the ML4812 with the exception of the operation of the slope compensation circuit. Please refer to the ML4812 data sheet for more information. The following calculations refer to Figure 12 in this data sheet. The component designators in the equations below refer to the following components in Figure 12: RT = R16, CT = C6. INPUT INDUCTOR (L1) SELECTION The central component in the regulator is the input boost inductor. The value of this inductor controls various critical operational aspects of the regulator. If the value is too low, the input current distortion will be high and will result in low power factor and increased noise at the input. This will require more input filtering. In addition, when the value of the inductor is low the inductor dries out (runs out of current) at low currents. Thus the power factor will decrease at lower power levels and/or higher line voltages. If the inductor value is too high, then for a given operating current the required size of the inductor core will be large and/or the required number of turns will be high. So a balance must be reached between distortion and core size. One more condition where the inductor can dry out is analyzed below where it is shown to be maximum duty cycle dependent. For the boost converter at steady state:
VIN VOUT = 1- DON
(4)
VIN(MAX) = 260V PIN(MIN) = 50W then: IIN(MIN)PEAK = 0.272A Step 2: Choose a minimum current at which point the inductor current will be on the verge of drying out. For this example 40% of the peak current found in step 1 was chosen.
(1)
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VREF IN R2 510k F1 C1 0.6F - B+ 380V L1 PGND D7 1N4148 NP T1 R6 4.75k UI ML4819 R11 91 C4 6800pF Q1 IRF840 R12 10
1 ISENSE A 2 OVP 3 GM OUT
STARTUP CIRCUIT OUT D5
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D1 - D4 + 1N5406 1N5406 POWER FACTOR CORRECTION R5 357k R7 357k R10 33k C5 1000pF CT 20 GND 19 VREF 18 PGND A 17 OUT A 16 VCC 15 C13 1F R17, 3 R18 65k VCC D14 D11 MUR150 D12 MUR150 T3 C11 1F T2 R19, 3k D10 1N4148 R21 3k D13 D83 -004 OUT B 14 PGND B 13 RAMP COMP 12 ILIM 11 R20 7.5 Q3 IRF840 VREF C9 0.1F C11 1F + D9 MUR110 T3 C10 330F 25VDC C6 1000pF D6 MUR850 B+ 380 VDC R8 4.53k C3 0.62F C2 330F 400VDC R9 27k C8 1
4 EA OUT A 5 INV A 6 ISINE 7 DUTY CYCLE 8 PWM B 9 ISENSE B 10 RT
PFC ENHANCEMENT
R1 330k
VREF
Q4 2N2222
R4 C7 12k 10F 35V
D8 3V
VREF
R3 5.6k
R13 4.7k
R14 4.7k
C12 1F
VIN+ +12V C16 1F C18 1500F VOUT- R22 10 R23, 100 R25 1 C14 2200pF R24 1 MOC 8102 C20 U3 TL431 0.1F C19 4.7F Q3 IRF840 R27 1.2k R26 1.5k U2
VREF D13
R15 4.3k
R16 15k
Figure 12. Typical Application, 180W Power Factor Corrected 12V Output Power Supply
R29 2.26k PWM REGULATOR
R28 8.66k
ML4819
9
ML4819
then: ILDRY = 100mA CURRENT SENSE AND SLOPE (RAMP) COMPENSATION COMPONENT SELECTION Slope compensation in the ML4819 is provided internally. A current equal to VCT/2(R18) is added to ISENSE A (pin 1). this is converted to a voltage by R10, adding slope to the sensed current through T1. The amount of slope compensation should be at least 50% of the downslope of the inductor current during the off time as reflected on pin 1. Note that slope compensation is a requirement only if the inductor current is continuous and the duty cycle is more than 50%. The highest inductor downslope is found at the point of inductor discontinuity:
diL VB - VIN DRY 380V - 20V = = = 0.18 A / s 2mH dt L
Step 3: The value of the inductance can now be found using previously calculated data.
VINDRY x DON(MAX) IL(DRY) x fOSC 20V x 0.95 = 2mH 100mA x 100kHz
L1 = =
(5)
The inductor can be allowed to decrease in value when the current sweeps from minimum to maximum value. This allows the use of smaller core sizes. The only requirement is that the ramp compensation must be adequate for the lower inductance value of the core so that there is adequate compensation at high current. Step 4: The presence of the ramp compensation will change the dry out point, but the value found above can be considered a good starting point. Based on the amount of power factor correction the value of L1 can be optimized after a few iterations. Gapped Ferrites, Molypermalloy, and Powdered Iron cores are typical choices for core material. The core material selected should have a high saturation point and acceptable losses at the operating frequency. One ferrite core that is suitable at around 200W is the #4229PL00-3C8 made by Ferroxcube. This ungapped core will require a total gap of 0.180" for this application. OSCILLATOR COMPONENT SELECTION The oscillator timing components can be calculated by using the following expression:
fOSC = 1.36 R T x CT
(9)
The downslope as reflected to the input of the PWM comparator is given by:
SPWM = VB - VIN DRY L1 x R11 NC
(10)
Where NC is the turns ratio of the current transformer (T1) used. In general, current transformers simplify the sensing of switch currents, especially at high power levels where the use of sense resistors is complicated by the amount of power they have to dissipate. Normally the primary side of the transformer consists of a single turn and the secondary consists of several turns of either enameled magnet wire or insulated wire. The diameter of the ferrite core used in this example is 0.5" (SPANG/Magnetics F41206-TC). The rectifying diode at the output of the current transformer can be a 1N4148 for secondary currents up to 75mA average. Current-sensing MOSFETs or resistive sensing can also be used to sense the switch current. In these cases, the sensed signal has to be amplified to the proper level before it is applied to the ML4819. The value of the ramp compensation (SCPWM) as seen at pin 1 is:
SCPWM = 2.5 x R 9 R16 x C6 x R18
(6)
For example: Step 1: At 100kHz with 95% duty cycle TOFF = 500ns calculate CT using the following formula:
t xI CT = OFF DIS = 1000pF VOSC
(11)
(7)
The required value for R18 can therefore be found by equating:
SCPWM = ASC x SPWM
Step 2: Calculate the required value of the timing resistor.
RT = 1.36 = 1.36 fOSC x CT 100kHz x 1000pF
where ASC is the amount of slope compensation and solving for R18.
= 13.6k. Choose R T = 14k.
(8)
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ML4819
The value of R9 (pin 3) depends on the selection of R2 (pin 6).
R2 = VIN(MAX) PEAK ISINE (PEAK) = 260 x 1.414 = 510k 0.72mA
VOLTAGE REGULATION COMPONENTS The values of the voltage regulation loop components are calculated based on the operating output voltage. Note that voltage safety regulations require the use of sense resistors that have adequate voltage rating. As a rule of thumb if 1/4W through-hole resistors are used, two of them should be put in series. The input bias current of the error amplifier is approximately 0.5A, therefore the current available from the voltage sense resistors should be significantly higher than this value. Since two 1/4W resistors have to be used the total power rating is 1/2W. The operating power is set to be 0.4W then with 380V output voltage the value can be calculated as follows:
R5 = (380V) / 0.4W = 360k
2
(12)
R9 >
VCLAMP x R2 4.8 x 510k = = 22k VIN(MIN) PEAK 80 x 1.414
(13)
Choose R9 = 27k The peak of the inductor current can be found approximately by:
ILPEAK = 1.414 x POUT 1.414 x 200 = = 3.14A VIN (MIN) RMS 90
(17)
Choose two 178k, 1% connected in series. (14) Then R6 can be calculated using the formula below:
R6 = VREF x R5 5V x 356k = = 4.747k VB - VREF 380V - 5V
Next select NC, which depends on the maximum switch current. Assume 4A for this example. NC is 80 turns.
R11 = VCLAMP x NC 4.9 x 80 = = 100 ILPEAK 4
(18)
(15)
Where R11 is the sense resistor, and VCLAMP is the current clamp at the inverting input of the PWM comparator. This clamp is internally set to 5V. In actual application it is a good idea to assume a value less than 5V to avoid unwanted current limiting action due to component tolerances. In this application VCLAMP was chosen as 4.8V. Having calculated R11 the value SPWM and of R18 can now be calculated:
SPWM = 380V - 20 x 100 = 0.225V / s 2mH 80
Choose 4.75k, 1%. One more critical component in the voltage regulation loop is the feedback capacitor for the error amplifier. The voltage loop bandwidth should be set such that it rejects the 120Hz ripple which is present at the output. If this ripple is not adequately attenuated it will cause distortion on the input current waveform. Typical bandwidths range anywhere from a few Hertz to 15Hz. The main compromise is between transient response and distortion. The feedback capacitor can be calculated using the following formula:
C8 = C8 = 1 3.142 x R5 x BW 1 = 0.44F 3.142 x 356k x 2Hz
(19)
R18 = R18 =
2.5 x R 9 ASC x SPWM x R T x CT 2.5 x 28.8k nF 0.7 x (0.225 x 10 ) x 14k x 1
6
30k
(16)
Choose R18 = 33k The following values were used in the calculation: R9 = 27k RT = 14k ASC = 0.7 CT = 1nF
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ML4819
OVERVOLTAGE PROTECTION (OVP) COMPONENTS The OVP loop should be set so that there is no interaction with the voltage control loop. Typically it should be set to a level where the power components are safe to operate. Ten to fifteen volts above VOUT seems to be adequate. This sets the maximum transient output voltage to about 395V. By choosing the high voltage side resistor of the OVP circuit the same way as above i.e. R7 = 356K then R8 can be calculated as:
R8 = VREF x R7 = 5V x 356k = 4.564k VOVP - VREF 395V - 5V
PWM SECTION The PWM section in Figure 12 is a two switch forward converter, shown in Figure 14 below for clarity. This fully clamped circuit eliminates the need for very high voltage MOSFETs. Flyback topology is also possible with the ML4819.
385VDC Q2 T2 D12
(20)
D11 T3
Choose 4.53k, 1%. Note that R5, R6, R7 and R8 should be tight tolerance resistors such as 1% or better.
ML4819 T2 Q3
OFF-LINE START-UP AND BIAS SUPPLY GENERATION The Start-Up circuit in Figure 12 can be either a "bleed resistor" (39k, 2W) or the circuit shown in Figure 13. The bleed resistor method offers advantage of simplicity and lowest cost, but may yield excessive turn-on delay at low line. When the voltage on pin 15 (VCC) exceeds 16V, the IC starts up. The energy stored on the C21 supplies the IC with running power until the supplemental winding on T3 can provide the power to sustain operation.
IN
Figure 14. Two-Switch Forward Converter This regulator (Figure 12) uses current mode control. Current is sensed through R24 and filtered for high frequency noise and leading edge transient through T23 and C14. The main regulation loop is through PWM B. The TL431 (U3) in the secondary serves as both the voltage reference and error amplifier. Galvanic isolation is provided by an optocoupler (U2) which provides a current command signal on pin 8. Loop compensation is provided by R29 and C20. The output voltage is set by:
R VOUT = 2.5 1+ 29 R28
START-UP CIRCUIT
R31 510k
R30 4.3k
(21)
R33 2k VREF R32 2k
Q6 IRF821 Q5 2N2222 C21 0.1 OUT D16 22V D15 1N4001 TO VCC
The control loop is compensated using standard compensation techniques. Current is limited to a threshold of 2A (1V on R24). The duty cycle is limited in this circuit to below 50% to prevent transformer (T3) core saturation. The maximum duty cycle limit of 45% is set using a threshold of VREF/2 on pin 7. the circuit in Figure 12 can be modified for voltage mode operation by utilizing the slope current which appears on pin 9 as show in figure 15 below. The ramp amplitude appearing on pin 9 will be:
VR = I R18 x R(V) 2
Figure 13. Start-Up Circuit ENHANCEMENT CIRCUIT The power factor enhancement circuit (inside the dotted lines) in Figure 11 is described in Application Note 11. It improves the power factor and lowers the input current harmonics. Note that the circuit meets IEC1000-3-2 specifications (with the enhancement circuit installed) on the harmonics by a large margin while correcting the input power factor to better than 0.99 under most steady state operating conditions.
(22)
where R18 is the slope compensation resistor. Since this circuit operates with a constant input voltage (as supplied by the PFC section) voltage feed-forward is unnecessary.
12
REV. 1.0 10/10/2000
ML4819
SLOPE COMP. IRSC
2
OSC CT C6
20
VREF
+ -
R13 DUTY CYCLE ILIM 1V ISENSE B - 0.7V +
9 7
+ -
11
FROM R23, C14 RV
R14
+ -
PWM B
8
FROM U2, R15
Figure 15. Voltage Mode Configuration
CONSTRUCTION AND LAYOUT TIPS High frequency power circuits require special care during breadboard construction and layout. Double sided printed circuit boards with ground plane on one side are highly recommended. All critical switching leads (power FET, output diode, IC output and ground leads, bypass capacitors) should be kept as small as possible. This is to minimize both the transmission and pickup of switching noise. There are two kinds of noise coupling; inductive and capacitive. As the name implies inductive coupling is due to fast changing (high di/dt) circulating switching currents. The main source is the loop formed by Q1, D6, and C3-C4. Therefore this loop should be as small as possible, and the above capacitors should be good, high frequency types. The second form of noise coupling is due to fast changing voltages (high dv/dt). The main source in this case is the drain of the power FET. The radiated noise in this case can be minimized by insulating the drain of the FET from the heatsink and then tying the heatsink to the source of the FET with a high frequency capacitor. The IC has two ground pins named PWR GND and Signal GND. These two pins should be connected together with a very short lead at the printed circuit board exit point. In general grounding is very important and ground loops should be avoided. Star grounding schemes are preferred.
REV. 1.0 10/10/2000
13
ML4819
Component Values/Bill of Materials for Figure 12
Reference C1, C3 C2 C4 C5, C6 C7 Description 0.6F, 630V Film (250 VAC) 330F 25V Electrolytic 6800pF 1KV Ceramic 1000pF 10F 35V R4 R5, R7 R6 R8 R9 R10, R18 R11 R12, R22 R13, R14 R15 R16 R17 R20 R21,R19 R23 R24, R25 R26 R27 R28 R29 R30 R32, R33 T1 Reference 12k 357k, 1% 4.57k, 1% 4.53k, 1% 27k 33k 91 10 4.7k 4.3k 15k 3 7.5 3k 100 1 1.5k 1.2k 8.66k, 1% 2.26k, 1% 2k, 1W 2k Spang F41206-TC or Siemens B64290-K45-X27 or X830 or Ferroxcube 768T188-38 NS = 80, NP = 1 Same core as T1 NS = NP = 15 bifilar Core: Ferroxcube 4229-3C8 Pri. 44 Turns #18 Litz wire Sec. 4 Turns of copper strip Aux. 2 Turns #24 AWG MOC8102 TL431 Description
C8, C11, C13, C15, C16 1F Ceramic C9, C20, C21 C10 C12, C17 C14 C18 C19 D1- D5 D6 D7, D10 D8 D9 D11, D12 D13 D15 D16, D14 F1 L1 0.1F Ceramic 1500F 25V Electrolytic 1F Ceramic 2200 pF 1500F 16V Electrolytic 4.7F 1N5406 MUR850 1N4148 3V Zener diode or 4 x 1N4148 in series MUR110 MUR150 D83-004K 1N4001 1N5818 or 1N5819 5A, 250V, 3AG 2mH, 4A IPEAK Core: Ferroxcube 4229-3CB 150 Turns #24 AWG 0.150" gap 10H Core: Spang OF 43019 UG00 8 Turns #15AWG gap 0.05" IRF840 2N2222 IRF821 330k 510k 5.6k
L2
T2 T3
Q1-Q3 Q4, Q5 Q6 R1 R2, R31 R3
U2 U3
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REV. 1.0 10/10/2000
ML4819
PHYSICAL DIMENSIONS inches (millimeters)
Package: P20 20-Pin PDIP
1.010 - 1.035 (25.65 - 26.29) 20
PIN 1 ID
0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.26)
0.060 MIN (1.52 MIN) (4 PLACES)
1 0.055 - 0.065 (1.40 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN)
0.170 MAX (4.32 MAX)
0.125 MIN (3.18 MIN)
0.016 - 0.022 (0.40 - 0.56)
SEATING PLANE
0 - 15
0.008 - 0.012 (0.20 - 0.31)
ORDERING INFORMATION
PART NUMBER ML4819CP ML4819CS (Obsolete) TEMPERATURE RANGE 0C to 70C 0C to 70C PACKAGE Molded DIP (P20) Molded SOIC (S20)
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com
REV. 1.0 10/10/2000
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
(c) 2000 Fairchild Semiconductor Corporation
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